toshiba developes circuit techniques for embedded SRAM
Posted on | November 23, 2011 | 1 Comment
Toshiba Corp has developed circuit techniques for embedded SRAM that operate in a wide supply voltage range, from 0.5V to one.0V, that effectively contribute to lower power consumption through electronic devices.
The test chip fabricated employs new techniques to ensure proper operation of SRAM even when the operating voltage is different. Additionally, cell failure rate will be reduced and operation itself has increased its speed. Toshiba has demonstrated these techniques in a 40nm 2Mb SRAM check chip at 0.5V operation.
Embedded SRAM in LSI for mobile equipment have multiple cells for information storage and should accomplish stable performance even if cell characteristics vary. Traditional SRAM techniques employ wordline choice signals for read/write operations. As operating conditions, such as transistor thresholds, temperature & voltage, vary, the optimum wordline voltage at which SRAM cells properly operate also changes.
Toshiba’s new circuit process predicts SRAM cell failure rate in actual time & automatically programs wordline voltage so that the cell memory is retained even when operating conditions vary. The result is a reduction in the cell failure rate to one-hundredth that of conventional SRAM. This new circuit process also eliminates the necessity to program the wordline level voltage chip by chip, which conventional SRAM requires
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February 3rd, 2013 @ 6:19 pm
There are several approaches that the embedded memory IP providers may incorporate to mitigate READ and WRITE failures that occur at low voltage operation where the Static Noise Margin is very small. These approaches may include techniques such as Read Assist, Write Assist, and use of Dual Voltage Rails.